Gate driver and display apparatus thereof

A display apparatus comprising:

• a display region;
• a non-display region surrounding the display region, and the non-display region comprising:
• at least one gate driver configured to generate a plurality of shifted pulse signals shifted in a specified phase;
• the at least one gate driver comprising:
• a plurality of unit circuits connected in a plurality of stages, each unit circuit configured to receive at least one external clock control signal and sequentially operate under an initial period and an operation period;
• and each unit circuit comprising:
• an output terminal, electrically connected to at least one external signal line, and configured to provide a shifted pulse signal to the connected corresponding at least one external signal line;
• an input transistor configured to output a high level voltage to a first node based on a trigger signal activating the unit circuit;
• an output transistor configured to output the shifted pulse signal to the output terminal in responding to the high level voltage of the first node, the shifted pulse signal being synchronous with the clock control signal;
• a gate electrode of the output transistor connected to the first node, a drain electrode of the output transistor receiving the clock control signal, and a source electrode of the output transistor connected to the output terminal;
• and
• a holding module configured to receive the trigger signal, a first control signal, and a second control signal;
• wherein when the initial period, the trigger signal is at a low level voltage, the first control signal and the second control signal are at same high level voltage, the holding module outputs the low level voltage to the output terminal based on the first control signal and the second control signal.