Secure logic chip for resisting hardware trojan induced leakage in combinational logics
AssigneeGovernment of the United States as Represented by the Secretary of the Air Force
InventorsYIYU SHI, TRAVIS SCHULZE, KEVIN KWIAT, CHARLES KAMHOUA
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Abstract
The invention is a secure logic chip with resistance to hardware Trojan induced data leakage. The invention solves the untrustworthy fabrication risk problem by introducing a secure logic chip design such that even when the design is entirely known to an attacker and a data leakage Trojan is injected subsequently, no useful information can be obtained. This invention contains several features including randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning a randomized encoded logic for split manufacturing.
Claims7
A secure logic chip for preventing data leakage, comprising:
- a chip having an input/output area communicating with an external area;
- said external area containing logic blocks;
- said input/output area including a random number generator;
- wherein said random number generator outputs a random value along a random rail;
- said random rail communicating with a first logic gate and a second logic gate;
- wherein said first logic gate converts said random logic value and a selected single rail input signal into dual-rail representation for said external area;
- said input/output area further comprising a multiplexer;
- wherein said multiplexer and said second logic gate covert an external dual rail signal from said external area into a single rail output signal.
A random rail as in claim 11, wherein said random rail, said first logic gate and said second logic gate are contained in their entirety within said input/output area.
Dependencies are inferred from the claim text.