Semiconductor fab's defect operating system and method thereof

A Semiconductor Fab's Defect Operating System comprises a memory unit and a data processing unit, wherein the memory unit is used to store each process layer's systematic random defect inspection data inputted from a semiconductor Fab and a IC design layout pattern from a IC design house, the characterized in that:

• the data processing unit operates each of the random defect inspection data through a coordinate conversion and a coordinate calibration, after each of the random defect inspection data is transferred to the IC design layout pattern coordinate, executing a size calibration for each of the random defect to obtain an image data file in each of the random defect in the IC design layout pattern coordinate region;
• the data processing unit executes a critical area analysis for each of the random defect calibrated to obtain the image data file in the IC designed layout pattern coordinate by screening out killer defects in the random defects;
• the data processing unit conducts an analysis for a test-failed item which is a bad die from a wafer yield sorting data to obtain a layer and area for each of the killer systematic defect in the IC design layout pattern;
• the data processing unit conducts a comparison analysis for the killer defects undergone the critical area analysis and the analysis of the test-failed item to check the layer and the area in the IC design layout pattern where the killer random defects are surely located on;
• the data processing unit transfers the image data file in the IC design layout pattern coordinate of the killer random defect into a random defect text and an image data file.

A Semiconductor Fab's Defect Operating System comprises a memory unit and a data processing unit, the memory unit is used to store every process layer's systematic defect inspection data imported from semiconductor Fab and the IC design layout pattern, and a wafer yield sorting data imported from IC design house, the system comprising:

• the data processing unit handles every layer's random defect inspection data through coordinate conversion and coordinate calibration, then, every random defect coordinate is converted to IC design layout pattern coordinate, execute defect size calibration for every random defect, and obtain the random defect data image file with defect in the IC design layout pattern coordinate data;
• the data processing unit executes critical area analysis on every random defect with calibrated defect size, screen the killer random defects out of the whole random defect, and obtain the killer random defects data image file with defect in the IC design layout pattern coordinate area;
• the data processing unit focus on the bad die from a wafer yield sorting data and conduct testing failure item's analysis, obtain the killer random defect, which causes testing failure, layer and zone area data with defect in the IC design layout pattern area;
• the data processing unit compares ‘the killer random defects (after critical area analysis) data image file with defect in the IC design layout pattern coordinate with the killer random defect (which causes testing failure) data file with defect in the IC design layout pattern coordinate area’, confirm the killer random defect layer and zone area that actually maps in the IC design layout pattern;
• and
• the data processing unit converts the killer random defects data image file with layer and zone area in the IC design layout pattern' into a random defect text and image data file.