Less-pessimistic static timing analysis for synchronous circuits
AssigneeSanDisk Technologies LLC
InventorsNorihiro Kamae, Minoru Yamashita, Biju Manuel
Life of this patent
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Abstract
A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.
Claims21
An apparatus comprising:
- a static timing analysis controller comprising:
- a feedback loop identification module configured to identify an invariable flip flop feedback loop of an integrated circuit design;
- and
- a timing violation identification module configured to identify hold violations in the integrated circuit design by ignoring the invariable flip flop feedback loops.
A method comprising:
- selecting, with a static timing analysis controller, a flip flop from a cell list for an integrated circuit design;
- identifying, with the static timing analysis controller, an invariable flip flop feedback loop of the flip flop;
- and
- calculating, with the static timing analysis controller, delays of a plurality of timing paths of the integrated circuit design by ignoring the invariable flip flop feedback loop.
A non-transitory computer readable storage medium storing computer instructions executable by a processor, the computer instructions comprising:
- instructions to identify a plurality of flip flops of an integrated circuit design;
- instructions to traverse feedback loops of the plurality of flip flops;
- instructions to determine a set of invariable flip flop feedback loops from among the feedback loops in response to the traversing;
- instructions to execute a timing update phase of a static timing analysis that ignores the set of invariable flip flop feedback loops;
- instructions to identify hold violations in response to execution of the timing update phase;
- and
- instructions to add buffers to the integrated circuit design in response to the identified hold violations.
Dependencies are inferred from the claim text.