Coherent placement of slotline mode suppression structures in coplanar waveguides for quantum devices

A computer-implemented method, comprising:

• determining, by a device operatively coupled to a processor, locations for mode suppression structures on a coplanar waveguide of a quantum chip;
• simulating, by the device, performance of the quantum chip based on a subset of the locations for the mode suppression structures and parameters of the quantum chip, and generating, by the device, a mode suppression structures placement model;
• generating, by the device, a template of specific coordinates for placement of a subset of the mode suppression structures on the quantum chip based on the mode suppression structures placement model;
• and
• employing, by the device, the template to drive an auto-bonder to install the subset of the mode suppression structures on the quantum chip at the specific coordinates defined by the template.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processor to cause the processor to:

• determine locations for mode suppression structures on a coplanar waveguide of a quantum chip;
• simulate performance of the quantum chip based on locations of a subset of the mode suppression structures and parameters of the quantum chip, and generate a mode suppression structures placement model;
• generate a template of specific coordinates for placement of the subset of the mode suppression structures on the quantum chip based on the mode suppression structures placement model;
• and
• employ the template to drive an auto-bonder to install the subset of the mode suppression structures on the quantum chip at the specific coordinates defined by the template.