Timing-adaptive, configurable logic architecture
AssigneeMellanox Technologies, Ltd.
InventorsUria Basher, Anton Rozen
Life of this patent
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Abstract
A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.
Claims10
A method for designing a logic circuit, the method comprising:
- providing an initial design of the logic circuit, comprising (i) at least first and second logic stages, and (ii) a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch;
- estimating timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed;
- based on the timing delays, making a decision whether or not the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit;
- and
- generating a final design of the logic circuit, in which the sequential component is either bypassed or not bypassed, depending on the decision.
A system, comprising:
- a memory;
- and
- a processor, which is configured to:
- retrieve from the memory an initial design of the logic circuit, comprising (i) at least first and second pipeline stages, and (ii) a sequential component, which is inserted between the first and second pipeline stages and comprises a flip-flop or a latch;
- estimate timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed;
- based on the timing delays, make or obtain from a user a decision whether or not the sequential component is to bypassed;
- and
- generate a final design of the logic circuit, in which the sequential component is either bypassed, or not bypassed, depending on the decision.
Dependencies are inferred from the claim text.