Design space exploration with bayesian inference

A system for physically fabricating an electronic circuit using design space exploration as part of a design process, the system comprising:

• a memory;
• a processor communicatively coupled to the memory, where the processor is configured to perform a) defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters;
• b) defining an output target to be optimized;
• c) generating a series of one or more test mask shapes to appear on a photo mask using the plurality of design space parameters;
• d) simulating at least one of a post lithography or etch on the series of one or more test mask shapes to produce simulation output values;
• e) feeding the simulation output values and corresponding design space parameters to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate;
• repeating steps a through e until a maximum or a minimum output is achieved due to the Bayesian inference algorithm duplicating combinations of design space parameters to investigate or not finding a new maximum or minimum output with any other combinations of design space parameters;
• and
• performing physical design synthesis with a computer to physically implement at least one electronic circuit based on the series of one or more test mask shapes using the plurality of design space parameters.

A computer program product for physically fabricating an electronic circuit using design space exploration as part of a design process, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:

• a) defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters;
• b) defining an output target to be optimized;
• c) generating a series of one or more test mask shapes to appear on a photo mask using the plurality of design space parameters;
• d) simulating at least one of a post lithography or etch on the series of one or more test mask shapes to produce simulation output values;
• e) feeding the simulation output values and corresponding design space parameters to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate;
• repeating steps a through e until a maximum or a minimum output is achieved due to the Bayesian inference algorithm duplicating combinations of design space parameters to investigate or not finding a new maximum or minimum output with any other combinations of design space parameters;
• and
• performing physical design synthesis with a computer to physically implement at least one electronic circuit based on the series of one or more test mask shapes using the plurality of design space parameters.