Apparatuses, methods, and systems for instructions of a matrix operations accelerator

A method comprising:

• decoding, with a decoder of a processor core, a single instruction into a decoded single instruction, wherein the processor core is coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of fused multiply accumulate circuits, the matrix operations accelerator circuit is coupled to a first plurality of registers that represents at least one first input two-dimensional matrix and a second plurality of registers that represents at least one second input two-dimensional matrix, and the single instruction includes a field that identifies a resultant storage;
• and
• executing the decoded single instruction with an execution circuit of the processor core to:
• switch the matrix operations accelerator circuit from a first mode where a respective output of each of a first proper subset of fused multiply accumulate circuits of the two-dimensional grid is transmitted downstream to a respective input of each of a second proper subset of fused multiply accumulate circuits of the two-dimensional grid to form output values from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the output values in the resultant storage, to a second mode where the respective output of each of the first proper subset of fused multiply accumulate circuits of the two-dimensional grid form first output values from a first subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the first output values in the resultant storage, and a respective output of each of the second proper subset of fused multiply accumulate circuits of the two-dimensional grid form second output values from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the second output values in the resultant storage.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• decoding, with a decoder of a processor core, a single instruction into a decoded single instruction, wherein the processor core is coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of fused multiply accumulate circuits, the matrix operations accelerator circuit is coupled to a first plurality of registers that represents at least one first input two-dimensional matrix and a second plurality of registers that represents at least one second input two-dimensional matrix, and the single instruction includes a field that identifies a resultant storage;
• and
• executing the decoded single instruction with an execution circuit of the processor core to:
• switch the matrix operations accelerator circuit from a first mode where a respective output of each of a first proper subset of fused multiply accumulate circuits of the two-dimensional grid is transmitted downstream to a respective input of each of a second proper subset of fused multiply accumulate circuits of the two-dimensional grid to form output values from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the output values in the resultant storage, to a second mode where the respective output of each of the first proper subset of fused multiply accumulate circuits of the two-dimensional grid form first output values from a first subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the first output values in the resultant storage, and a respective output of each of the second proper subset of fused multiply accumulate circuits of the two-dimensional grid form second output values from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the second output values in the resultant storage.