Pipelined configurable processor

A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising:

• a thread data store;
• a plurality of configurable execution units;
• a configurable routing network for connecting the thread data store to the execution units;
• a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units;
• and
• a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle;
• the circuit being configured to:
• (i) associate each thread with a configuration instance;
• and (ii) configure each of the plurality of pipeline sections at each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

A method for handling multiple threads simultaneously in a configurable processing circuit that comprises a thread data store, a plurality of configurable execution units, a configurable routing network for connecting the thread data store to the execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections, the method comprising:

• associating each thread with a configuration instance that defines a configuration of the routing network and a configuration of one or more of the plurality of execution units;
• causing each thread to propagate from one pipeline section to the next at each clock cycle;
• and
• configuring each of the plurality of pipeline sections at each clock cycle so that each pipeline section is configured in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.