Configurable network-on-chip for a programmable device
AssigneeXilinx, Inc.
InventorsIan A. Swarbrick, Sagheer Ahmad, Ygal Arbel, Dinesh D. Gaitonde
Life of this patent
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Abstract
An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
Claims19
A programmable integrated circuit (IC), comprising:
- a processor;
- a plurality of endpoint circuits;
- a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI);
- wherein the processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
The programmable IC of claim 1, wherein each NMU comprises:
- a master interface coupled to an endpoint circuit of the plurality of endpoint circuits;
- packetizing circuitry coupled to the master interface configured to packetize inbound data received at the master interface;
- and
- clock management circuitry configured to perform rate matching and asynchronous data crossing between a clock domain of the master interface and a clock domain of the NoC. The programmable IC of claim 6, wherein each NMU further comprises:
- quality of service (QoS) circuitry configured to perform rate limiting of packets into the NoC;
- and
- virtual channel (VC) mapping circuitry configured to map the packets to a virtual channel of a plurality of virtual channels.
A method of programming a network on chip (NoC) in a programmable integrated circuit (IC), comprising:
- receiving first programming data at a processor in the programmable IC at boot time;
- loading the programming data to registers in the NoC through a NoC peripheral interface (NPI) to create physical channels between NoC master units (NMUs) and NoC slave units (NSUs) in the NoC;
- and
- booting the programmable IC.
A method of processing a request from an endpoint circuit in a network on chip (NoC) of a programmable integrated circuit (IC), comprising:
- receiving the request at a master interface of a NoC master unit (NMU) in the NoC;
- packetizing data of the request at the NMU;
- sending the packetized data to a NoC slave unit (NSU) in the NoC through one or more NoC packet switches (NPSs);
- de-packetizing the packetized data at the NSU;
- and
- providing de-packetized data to a slave interface of the NSU.
Dependencies are inferred from the claim text.