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US 2020/0026667 A1Published application
Write access control for double data rate write-x/datacopy0 commands
AssigneeQUALCOMM Incorporated
InventorsDexter Tamio CHUN, Yanru LI
Life of this patent
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Abstract
In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.
Claims37
An apparatus comprising:
- an execution engine access (EE) controller and a Dynamic Random Access Memory (DRAM) controller,
- wherein the EE controller is configured to:
- receive an indirect access command on a control path, the indirect access command being a command to access a DRAM device and in which at least a part of the command is received on a path other than on a data path, and
- translate a target address of the indirect access command, and
- wherein the DRAM controller is configured to:
- determine whether to allow or block the indirect access command based on the translated target address,
- transmit the indirect access command to a DRAM device when it is determined that the indirect access command is to be allowed, and
- block the indirect access command from being transmitted to the DRAM device when it is determined that the indirect access command is to be blocked, and
- wherein the DRAM device is coupled to the apparatus over a DRAM link, and
- wherein the indirect access command is transmitted over the DRAM link when it is determined that the indirect access command is to be allowed.
7 more elements
A method comprising:
- receiving, by an execution engine access (EE) controller of a host, an indirect access command on a control path, the indirect access command being a command to access a Dynamic Random Access Memory (DRAM) device and in which at least a part of the command is received on a path other than on a data path;
- translating, by the EE controller, a target address of the indirect access command;
- determining, by a DRAM controller of the host, whether to allow or block the indirect access command based on the translated target address;
- transmitting, by the DRAM controller, the indirect access command to a DRAM device when it is determined that the indirect access command is to be allowed;
- and
- blocking, by the DRAM controller, the indirect access command from being transmitted to the DRAM device when it is determined that the indirect access command is to be blocked, and
- wherein the DRAM device is coupled to the host over a DRAM link, and
- wherein the indirect access command is transmitted over the DRAM link when it is determined that the indirect access command is to be allowed.
5 more elements
An apparatus comprising:
- an execution engine access (EE) controller and a Dynamic Random Access Memory (DRAM) controller,
- wherein the EE controller comprises:
- means receiving an indirect access command, the indirect access command being a command to access a DRAM device and in which at least a part of the command is received on a path other than on a data path, and
- means for translating a target address of the indirect access command,
- wherein the DRAM controller comprises:
- means for determining whether to allow or block the indirect access command based on the translated target address;
- means for transmitting the indirect access command to the DRAM device when it is determined that the indirect access command is to be allowed;
- and
- means for blocking the indirect access command from being transmitted to the DRAM device when it is determined that the indirect access command is to be blocked, and
- wherein the DRAM device is coupled to the apparatus over a DRAM link, and
- wherein the indirect access command is transmitted over the DRAM link when it is determined that the indirect access command is to be allowed.
8 more elements
Dependencies are inferred from the claim text.