Cache memory, memory system including the same, and eviction method of cache memory
AssigneeSK hynix Inc.
InventorsSeung-Gyu JEONG, Dong-Gun KIM, Jung-Hyun KWON, Young-Suk MOON
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Abstract
In a cache memory used for communication between a host and a memory, the cache memory may include a plurality of cache sets, each comprising: a valid bit; N dirty bits; a tag; and N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host, wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.
Claims19
A cache memory for communication between a host and a memory, the cache memory comprising:
- a plurality of cache sets, each comprising:
- a valid bit;
- N dirty bits;
- a tag;
- and
- N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host,
- wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.
An eviction method of a cache memory for communication between a host and a memory, the eviction method comprising:
- giving a score to each of a plurality of cache sets on the basis of time required for evicting the corresponding cache set;
- and
- evicting a cache set determined from among the plurality of cache sets based the score given to each of the plurality of cache sets,
- wherein data chunk sizes of the host and the memory are different.
A memory system comprising:
- a memory configured to have a data chunk size N times as large as a data chunk size of a host, where N is an integer greater than or equal to 2;
- a cache memory configured for communication between the host and the memory and to include a plurality of cache sets;
- a hit/miss check circuit configured to check hit or miss of the cache memory;
- an eviction circuit configured to decide a cache set to be evicted among the plurality of cache sets and evict the decided cache set when an eviction operation of the cache memory is required;
- and
- an operation control circuit configured to control a read operation and a write operation of the memory,
- wherein each of the plurality of cache sets comprises:
- a valid bit;
- N dirty bits;
- a tag;
- and
- N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to the data chunk size of the host.
A system comprising:
- a host suitable for interfacing data of a first chunk size;
- a memory suitable for interfacing data of a second chunk size that is N times as large as the first chunk size, where N is an integer greater than or equal to 2;
- and
- a cache memory suitable for interfacing data between the host and the memory, the cache memory including at least one cache set,
- wherein the at least one cache set comprises
- a plurality of data sets for storing data of the second chunk size, each for storing data of the first chunk size, and
- a set of dirty bits corresponding to the plurality of data sets respectively, each set of dirty bits indicating whether data of the corresponding data set is identical to data of the memory.
Dependencies are inferred from the claim text.