Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning

A computing system, comprising:

• a processor;
• a multi-level memory, the multi-level memory comprising an upper level that is to act as a cache for the lower level;
• a memory controller coupled between the processor and the multi-level memory, the memory controller comprising circuitry to determine:
• i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion;
• ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address;
• iii) a partner slot of the slot in the cache in response to the miss;
• iv) whether there is a hit or miss in the partner slot in the cache for the request.

A method, comprising:

• performing the following with a memory controller that is interfaces with a multi-level memory having an upper level and a lower level where the upper level acts as a cache for the lower level:
• i) determining an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion;
• ii) determining a miss in the cache for the request because the slot is pinned with data from another address that competes with the address;
• iii) determining a partner slot of the slot in the cache in response to the miss;
• iv) determining whether there is a hit or miss in the partner slot in the cache for the request.