Memory Circuit and Cache Circuit Configuration

A cache memory die, comprising:

• a substrate;
• a predetermined number of sets of memory cells on the substrate;
• a first set of input/output terminals on a first surface of the cache memory die, the first set of input/output terminals configured to be coupled to a primary memory circuit outside the cache memory die, wherein the primary memory circuit is on a die different from the cache memory die;
• and
• a second set of input/output terminals on a second surface of the cache memory die, a first portion of the second set of input/output terminals being pin-to-pin compatible with the first set of input/output terminals, and a second portion of the second set of input/output terminals being not corresponding to any input/output terminal on the first surface of the cache memory die, wherein the second portion of the second set of input/output terminals is disposed between the first portion and the sets of memory cells.

A cache circuit, comprising:

• a first die, comprising:
• a predetermined number of sets of memory cells;
• a first set of terminals on a first surface of the first die, the first set of terminals being configured to be coupled to a primary memory circuit outside the cache circuit, wherein the primary memory circuit is on a die or a stack of dies different from the first die;
• a second set of terminals on a second surface of the first die, a first portion of the second set of terminals being pin-to-pin compatible with the first set of terminals and a second portion of the second set of terminals not being configured for electrical coupling to the primary memory circuit, wherein the second portion is disposed at a periphery of the first portion;
• and
• a second die comprising a memory controller circuit in communication with the primary memory circuit through the first die.