Semiconductor memory device
AssigneeLapis Semiconductor Co., Ltd.
InventorToshiharu OKADA
Life of this patent
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Abstract
A semiconductor memory device has a memory cell array area including a normal area including memory blocks and a redundant memory area including a redundant block which is a replacement target of a defective block among memory blocks; a storage unit storing address information indicating a position of the defective block in the normal area and address information indicating a position of the redundant block being the replacement target of the defective block, both being in association with each other as a first information; and an output circuit outputting a data row exhibiting a positional relation between the defective block and a memory block other than the defective block in the normal area based on the first information stored in the storage unit in response to the data read signal.
Claims5
A semiconductor memory device comprising:
- a memory cell array unit including
- a normal memory area including a plurality of memory blocks each including a plurality of memory cells and
- a redundant memory area including a redundant block which is a replacement target of a defective block among a plurality of memory blocks;
- a storage unit that stores address information indicating a position of the defective block in the normal memory area and address information indicating a position of the redundant block which is the replacement target of the defective block, both the address information being in association with each other as a first information;
- and
- an output circuit that outputs a data row having binary data exhibiting, for at least a partial area of the normal memory area, a positional relation between the defective block and a memory block other than the defective block in the normal memory area based on the first information stored in the storage unit in response to a data read signal.
A semiconductor memory device comprising:
- a memory cell array unit including
- a normal memory area including a plurality of memory blocks each including a plurality of memory cells and
- a redundant memory area including a redundant block which is a replacement target of a defective block among a plurality of memory blocks;
- a storage unit that stores address information indicating a position of the defective block in the normal memory area and address information indicating a position of the redundant block which is the replacement target of the defective block, both the address information being in association with each other as a first information;
- and
- a fixed-value writing circuit, based on the first information stored in the storage unit in response to a data write start signal, writes data of one value of binary data to the redundant block corresponding to the defective block, and writes the data of the other value to a memory block other than the defective block in the normal memory area.
Dependencies are inferred from the claim text.