Hybrid iterative error correcting and redundancy decoding operations for memory sub-systems

A system comprising:

• a plurality of memory components;
• and
• a processing device, operatively coupled with the plurality of memory components, to:
• read data stored on each of a plurality of memory components;
• identify that corresponding data stored on a number of the plurality of memory components cannot be decoded using an error correction code (ECC) decoding operation;
• determine whether the number of the plurality of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition;
• and
• responsive to determining that the number of the plurality of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies the threshold condition, perform a redundancy error correction decoding operation to correct the data stored on each of the plurality of memory components.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

• read a plurality of data blocks from a plurality of memory components;
• perform a redundancy error correction decoding operation on the plurality of data blocks to correct a particular data block of the plurality of data blocks that includes an error;
• and
• responsive to correcting the particular data block that includes the error, perform a redundancy reconstruction operation to reconstruct data of other data blocks of the plurality of data blocks that include an error.