Die-level error recovery scheme
AssigneeMicron Technology, Inc.
InventorReshmi Basu
Life of this patent
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Abstract
Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board that has memory devices each disposed on a planar surface of the printed circuit board. Each memory device may include two or more memory die, channels communicatively coupled the two or more memory die, and a memory controller communicatively coupled to the plurality of channels. The memory controller may deterministically maintain a die-level redundancy scheme via data transmission through the plurality of channels. The memory controller may also generate parity data associated with the two or more memory die in response to a data write event.
Claims20
An apparatus, comprising:
- a printed circuit board;
- a plurality of memory devices each disposed on a planar surface of the printed circuit board, wherein each memory device of the plurality of memory devices comprises two or more memory die;
- a plurality of channels communicatively coupled to each memory device of the plurality of memory devices, wherein each channel of the plurality of channels are associated with one of the two or more memory die of each memory device;
- and
- a memory controller communicatively coupled to the plurality of channels, wherein the memory controller is configured to maintain a die-level redundancy scheme via data transmission through the plurality of channels, wherein the memory controller is configured to generate parity data in response to a data write event.
A method, comprising:
- identifying a data write event at a first memory die of a memory device on a module that comprises a plurality of multi-die packaged memory devices;
- generating, in response to the identified data write event, an exclusive-or (XOR) result using an XOR logic operation on data that corresponds to the first memory die of the memory device;
- writing the XOR result as parity data to a second memory die of the memory device;
- determining that the first memory die of the memory device experienced a data error;
- and
- restoring the data that corresponds to the first memory die of the memory device using an inverse of the XOR logic operation on the parity data from the second memory die of the memory device.
A memory module, comprising:
- a plurality of memory devices comprising a first subset of memory die and a second subset of memory die;
- a plurality of channels communicatively coupled to each of the plurality of memory devices;
- and
- a memory controller communicatively coupled to each of the plurality of channels, wherein the memory controller is configured to:
- perform a data read/write operation via the plurality of channels;
- determine that data stored in the first subset of memory die changed;
- determine parity data indicative of data stored in the first subset of memory die based at least in part on determining that the data stored in the first subset of memory die changes;
- store the parity data in the second subset of memory die;
- determine that a data loss event occurred;
- and
- recreate lost data using the parity data and data stored in the first subset of memory die based at least in part on determining that the data loss event occurred.
Dependencies are inferred from the claim text.