Two die system on chip (soc) for providing hardware fault tolerance (hft) for a paired soc

At least one machine-readable medium including instructions for hardware fault tolerance, which when executed on a machine, cause the machine to perform operations comprising:

• in response to receiving an indication of a first error from a first die, sending a signal to de-energize first output data from a first processing logic, wherein the first die comprises the first processing logic;
• in response to receiving an indication of a second error from a secondary device, sending a signal to de-energize second output data of the secondary device;
• receiving first cross-comparison data from the first die;
• receiving second cross-comparison data from the secondary device;
• and
• in response to a comparison of first cross-comparison data with second cross-comparison data indicating an error and not receiving the first error or the second error, sending a signal to de-energize the first output data and the second output.

A method for hardware fault tolerance, the method comprising:

• in response to receiving an indication of a first error from first processing logic of a first die, sending a signal to de-energize first output data from the first processing logic;
• in response to receiving an indication of a second error from a secondary device, sending a signal to de-energize second output data of the secondary device;
• receiving first cross-comparison data from the first die;
• receiving second cross-comparison data from the secondary device;
• and
• in response to a comparison of first cross-comparison data with second cross-comparison data indicating an error and not receiving the first error or the second error, sending a signal to de-energize the first output data and the second output.