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US 2020/0026572 A1Published application
Apparatuses and methods to determine timing of operations
AssigneeMicron Technology, Inc.
InventorJeremiah J. Willcock
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. The method includes applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource.
Claims20
A method, comprising:
- receiving a command from a controller to move data from a source location in a memory device to a destination location in the memory device via an input/output (I/O), wherein the memory device comprises:
- an array of memory cells;
- sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and compute components configured to implement computation operations and memory read and write operations;
- and
- timing circuitry coupled to the array and sensing circuitry, the timing circuitry configured to provide conflict free timing for the computation operations and the memory operations on the sensing circuitry;
- receiving data values from the source location to a corresponding number of the sense amplifiers or of the compute components in the sensing circuitry;
- and
- moving the source location data values from the sensing circuitry via the I/O line to the destination location for a memory operation.
5 more elements
An apparatus, comprising:
- a memory device comprising:
- an array of memory cells;
- sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and compute components configured to implement computation operations and memory read and write operations;
- timing circuitry coupled to the array and sensing circuitry, the timing circuitry configured to provide conflict free timing for the computation operations and the memory operations on the sensing circuitry;
- and
- a source location and a destination location coupleable via an input/output (I/O) line shared by the source location and the destination location;
- wherein the memory device is configured to:
- receive a command from a controller to move data from the source location to the destination location;
- receive data values from the source location to a corresponding number of the sense amplifiers or of the compute components in the sensing circuitry;
- and
- move the source location data values from the sensing circuitry via the I/O line to the destination location for a memory operation.
8 more elements
An apparatus, comprising:
- a plurality of subarrays of memory cells;
- sensing circuitry coupled to the plurality of subarrays via a plurality of columns of the memory cells, the sensing circuitry including a sense amplifier and a compute component coupled to each of the columns;
- an input/output (I/O) line shared by and configured to selectably couple a source location and a destination location to move the data;
- a controller coupled to the plurality of subarrays and the sensing circuitry and configured to execute a command to move the data from the source location to the destination location;
- and
- timing circuitry associated with the controller and coupled to the sensing circuitry, the timing circuitry configured to schedule access for processing computation operations and read and write operations on the sensing circuitry.
3 more elements
Dependencies are inferred from the claim text.