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US 2020/0026519 A1Published application
Processor trace extensions to facilitate real-time security monitoring
AssigneeIntel Corporation
InventorsSalmin Sultana, Beeman Strong, Ravi Sahita
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Abstract
Embodiments described herein provide for a computing device comprising a hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction.
Claims20
A computing device comprising:
- a hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the hardware processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction.
A computing system comprising:
- a memory device;
- a hardware processor coupled to the memory device, the hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the hardware processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction and the processor trace packet is output to the memory device.
A method performed on a processor device, the method comprising:
- reading a processor trace configuration for the processor device, wherein reading the processor trace configuration for the processor device includes reading a first bit in a first configuration register to determine whether output of processor trace packets is enabled for the processor device and reading a second bit in a second configuration register to determine whether a processor trace packet is to be output for an instruction;
- detecting retirement of an instruction on the processor device, wherein the instruction is a retired instruction in a set of non-deterministic control flow transfer instructions;
- in response to a determination that the processor trace packet is enabled for the retired instruction, generating the processor trace packet for the retired instruction;
- and
- outputting the processor trace packet to memory coupled with the processor device.
2 more elements
Dependencies are inferred from the claim text.