US 2020/0026497 A1 · COMPUTATION CIRCUIT, COMPUTATION DEVICE AND SYSTEM INCLUDING THE SAME

Abstract

A computation circuit includes a plurality of processing elements and a common accumulator. The plurality of processing elements are sequentially coupled in series, and performs a multiply and accumulate (MAC) operation on a weight signal and at least one of two or more input signals received in each unit cycle. The common accumulator is sequentially and cyclically coupled to first to Kth processing elements among the plurality of processing elements, and configured to receive a computation value outputted from a processing element coupled thereto among the first to Kth processing elements, and store computation information. The K is decided based on values of the two or more input signals and the number of guard bits included in one processing element.

Claims21

Dependent claims

A computation circuit comprising:

a plurality of processing elements sequentially coupled in series, and configured to perform a multiply and accumulate (MAC) operation on a weight signal and at least one of two or more input signals received in each unit cycle;
and
a common accumulator sequentially and cyclically coupled to first to Kth processing elements among the plurality of processing elements, and configured to receive a computation value outputted from a processing element among the first to Kth processing elements, and store computation information including the computation value,
wherein K is determined based on values of the two or more input signals and the number of guard bits corresponding to one processing element.

1 more element

A computation circuit comprising:

a plurality of processing elements, each configured to receive at least one of two or more input signals in each unit cycle, and perform a multiply and accumulate (MAC) operation on a weight signal and at least one of the two or more input signals to generate a computation value;
and
a common accumulator configured to store computation values generated by the plurality of processing elements as plural pieces of computation information, respectively, coupled to each of the plurality of processing elements in each unit cycle in which the number of accumulations in the corresponding processing element reaches a threshold value, and configured to update computation information related to one processing element among the plurality of processing elements by accumulating a computation value outputted from the one processing element and a value corresponding to the computation information related to the one processing element.

Dependencies are inferred from the claim text.

Computation circuit, computation device and system including the same

Life of this patent

Computation circuit, computation device and system including the same

Life of this patent

Abstract

Claims21