Programmable Device Implementing Fixed and Floating Point Functionality in a Mixed Architecture

Digital signal processing (DSP) circuitry, comprising:

• one or more inputs;
• one or more outputs;
• a common processing pipeline from the one or more inputs to the one or more outputs;
• and
• mixed architecture circuitry configured to selectively implement both fixed-point operations and floating-point operations via the common processing pipeline.

A method, comprising:

• selecting a mode of operation for a digital signal processing (DSP) block from a plurality of operations, wherein the plurality of operations comprise both fixed-point operations and floating-point operations implemented via a common processing pipeline;
• and
• in response to selecting the mode of operation, configuring a set of multiplexers of the DSP circuitry;
• and
• performing the mode of operation using the configured set of multiplexers.

A configurable specialized programming block, comprising:

• a first set of input registers;
• a set of interstage registers;
• an output register bank;
• a first circuitry stage, configured to:
• receive a first input from the first set of input registers;
• process the first input and provide a first output to the set of interstage registers;
• a second circuitry stage, configured to:
• receive a second input from the set of interstage registers;
• process the second input and provide a second output to the output register bank;
• wherein the first circuitry stage and the second circuitry stage are on a common processing pipeline and together are selectively configurable to selectively implement both fixed-point operations and floating-point operations via the common processing pipeline.