Memory system with parity cache scheme and method of operating such memory system
AssigneeSK hynix Inc.
InventorsJeffrey SONG, Sean LEE
Life of this patent
Estimating the term…
Abstract
Within a memory system, architecture and operations for processing commands in a parity cache scheme support more open blocks taking into account cost and performance. Dynamic random access memory space holds parity buffers of all open blocks and communicates with a cache and cache controller. An open block queue (OBQ) accumulates commands in separate queues for each open block to increase cache hit rate. Open block counters keep track of the number of commands for each OBQ to facilitate arbitration. A unique identification (ID) is given for each open block.
Claims17
A memory system, comprising:
- a memory device that includes a plurality of open blocks, each having a unique identifier;
- and
- a memory controller including:
- dynamic random access memory (DRAM) configured with a plurality of parity buffers sized to accommodate all data of all of the open blocks,
- a cache and a cache controller in communication with the DRAM,
- a plurality of open block queues corresponding to the plurality of open blocks respectively, each open block queue configured to accumulate commands for the corresponding open block,
- a plurality of open block counters, one associated with each of the plurality of open blocks, each open block counter being configured to maintain an on-going count of the number of commands from the corresponding open block forwarded for processing,
- a plurality of die queues corresponding to the plurality of open block queues respectively, and
- an arbiter configured to arbitrate with respect to the open block queues to determine an order in which commands in the plurality of open block queues are to be processed.
A command processing system, comprising:
- an arbiter configured to arbitrate with respect to open block queues, each of which holds a group of commands, to select one of the open block queues based on current counts of a number of commands forwarded from each of the open block queues for processing;
- die queues, one associated with each of the open block queues, to receive commands forwarded from the respective open block queues;
- and
- a command processor for processing commands from the die queues.
A method for processing commands in a memory system including a plurality of open blocks, the method comprising:
- sending each of plurality of commands received by the memory system to one of a plurality of open block queues, each command containing a tag identifying a particular one of the open blocks;
- arbitrating among the open block queues to select one of the open block queues based on a set of rules that are selectively applied to increase cache hit rate;
- forwarding the commands in the selected open block queue for processing;
- increasing a count of a total number of commands forwarded for the selected open block queue by the number of commands forwarded in the forwarding operation;
- and
- decreasing the count after the commands from the selected open block queue are processed by the same number by which the count was increased in the increasing operation.
Dependencies are inferred from the claim text.