Data access request specifying enable vector
AssigneeArm Limited
InventorAndrew David TUNE
Life of this patent
Estimating the term…
Abstract
An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.
Claims15
An integrated circuit comprising:
- a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion;
- and
- a control node responsive to the data access request to control at least one destination node to service at least one data access transaction, each data access transaction associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.
A control node for an integrated circuit, comprising:
- interface circuitry to receive, from a requesting node, a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion;
- and
- control circuitry responsive to the data access request to control at least one destination node to service at least one data access transaction, each data access transaction associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.
A method for controlling data access transactions in an integrated circuit, comprising:
- receiving, from a requesting node of the integrated circuit, a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion;
- and
- in response to the data access request, controlling at least one destination node to service at least one data access transaction, each data access transaction associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.
Dependencies are inferred from the claim text.