Phase locked loop using direct digital frequency synthesizer

A phase locked loop (PLL) using a phase-locked direct digital synthesizer, comprising:

• a free-running oscillator configured to generate a free-running oscillation signal;
• a phase-locked direct digital synthesizer configured to generate an output clock signal and an output phase signal whose phases are locked, using the oscillation signal;
• and
• a phase interpolator configured to reduce out-of-band noise by processing the output clock signal,
• wherein the phase-locked direct digital synthesizer comprises:
• a sampling D flip-flop configured to sample the output phase signal with a synchronization reference clock signal, and output a phase difference signal corresponding to a phase difference between the output clock signal and the synchronization reference clock signal;
• a digital loop filter configured to generate a first frequency code for adjusting the frequency of the output clock signal by filtering the phase difference signal;
• a rotational accumulator configured to accumulate a sum frequency code in each period of the oscillation signal through a modulus method, the sum frequency code corresponding to the sum of the first frequency code and a second frequency code, and output the most significant bit (MSB) of the accumulated output value as the output clock signal;
• a retimer configured to generate the synchronization reference clock signal synchronized with the oscillation signal by sampling the reference clock signal with the oscillation signal;
• and
• a coarse frequency lock configured to generate the second frequency code and output the second frequency code to an input side of the rotational accumulator, in order to prevent harmonic lock which occurs when the output clock signal is sub-sampled.