Design-For-Test for Asynchronous Circuit Elements

A method comprising:

• implement copies of a scannable storage element, wherein each copy represents a point in time in a model of a circuit;
• implement, in the model, fault injection logic to inject a fault;
• determine a scan pattern to test for the fault based on the model;
• load the scan pattern into a physical implementation of the circuit;
• and
• perform a scan test on the physical implementation of the circuit using the scan pattern to detect the fault.

A method comprising:

• receiving a data signal at a first storage element;
• storing a first value based on the data signal at the first storage element;
• storing a second value at a scan latch, the second value being based on a scan pattern;
• selecting between the first value and the second value to provide at an output of a circuit via a path select multiplexer;
• and
• inhibiting the second value from propagating to the path select multiplexer while the scan latch is being loaded with the second value.