Hardware-based local-state retention fault detection

An integrated circuit comprising:

• a substrate comprising a circuit, the circuit comprising a scan controller, the scan controller comprising:
• memory and circuitry coupled to the memory, the circuitry configured to:
• in response to a first signal, send a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry;
• cycle through the scan chain obtaining state retention data from the state retention elements;
• determine an error detection code from the state retention data;
• store the error detection code in the memory;
• and
• send a third signal, the third signal indicating that the error detection code has been determined.

At least one machine-readable medium including instructions for a scan controller, which when executed on a machine, cause the machine to perform operations comprising:

• sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry, in response to a first signal:
• cycling through the scan chain obtaining state retention data from the state retention elements;
• determining an error detection code from the state retention data;
• storing the error detection code in the memory;
• and
• sending a third signal, the third signal indicating that the error detection code has been determined.

A method performed by an apparatus of a scan controller, the method comprising:

• sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry, in response to a first signal;
• cycling through the scan chain obtaining state retention data from the state retention elements;
• determining an error detection code from the state retention data;
• storing the error detection code in the memory;
• and
• sending a third signal, the third signal indicating that the error detection code has been determined.