# US 2020/0025824 A1 · Receiver equalization and stressed eye testing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0025824 A1 - Document ID: US20200025824A1 - Status: Published application - Kind: A1 - Application number: 16/039,945 - Filed: 2018-07-19 - Published: 2020-01-23 - Earliest claimed: 2018-07-19 - Assignees: Futurewei Technologies, Inc. - Applicants: Futurewei Technologies, Inc. - Inventors: Gang Zhao; Yongyao Li; Xusheng Liu - Web page: https://patentgrep.com/patent/US20200025824A1 ## CPC - G01R 31/3171: {BER [Bit Error Rate] test} - G01R 31/3191: {Calibration} - G11C 29/022: {in I/O circuitry} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/50: Marginal testing, e.g. race, voltage or current testing - G11C 29/56004: {Pattern generation} - G11C 29/56008: {Error analysis, representation of errors} - G11C 29/56012: {Timing aspects, clock generation, synchronisation} - G11C 29/56016: {Apparatus features} - H04L 1/14: in which the signals are sent back to the transmitter to be checked {; echo systems} - H04L 1/203: {Details of error rate determination, e.g. BER, FER or WER} - H04L 1/243: {at the transmitter, using a loop-back} - G11C 2029/5002: {Characteristic} - G11C 2029/5602: {Interface to device under test} - G11C 2029/5604: {Display of error information} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate. ## Claims ### Claim 1 A system for conducting receiver link equalization and bit error rate (BER) testing for an electronic device using a bit error rate tester (BERT), the system comprising: an electrical validation board having one or more pairs of data traces adapted to connect to an electronic device under test; and a calibration load board adapted to connect to the one or more pairs of data traces of the electrical validation board to receive a data pattern with jitter and noise injected from the BERT for transmission to the electronic device under test and to transmit the data pattern back to the BERT for calculation of a bit error rate. ### Claim 2 (depends on 1) The system of claim 1, wherein the one or more pairs of data traces comprises two or more pairs of data traces where each pair of data traces has a different length to cause different delay and inter-symbol interference effects when a data pattern is provided to the electronic device under test via one of the pairs of data traces. ### Claim 3 (depends on 1) The system of claim 1, wherein the electrical validation board includes a clock bus and a command and address (CA) bus, and wherein a loopback function is provided by connecting an output of the electronic device under test to the clock bus and the CA bus of the electrical validation board, whereby the data pattern received by the electronic device under test is sent back through CA and clock ports of the device under test and transmitted through the CA and clock buses of the electrical validation board and compliance load board back to the BERT. ### Claim 4 (depends on 1) The system of claim 1, wherein the electrical validation board includes one or more of Command, Control, Data, Response, and other output buses, and wherein a loopback function is provided by connecting an output of the electronic device under test to one or more of the Command, Control, Data, Response, and other output buses of the electrical validation board, whereby the data pattern received by the electronic device under test is sent back through one or more of Command, Control, Data, Response, and other output ports of the device under test and transmitted through one or more of the Command, Control, Data, Response, and other output buses of the electrical validation board and compliance load board back to the BERT. ### Claim 5 (depends on 1) The system of claim 1, wherein the one or more pairs of data traces of the electrical validation board are of equal length, further comprising an inter-symbol interference board disposed between the BERT and the calibration load board so as to receive the data pattern from the BERT, the inter-symbol interference board having respective pairs of data traces of varied lengths to provide the different delay and inter-symbol interference effects to the electronic device under test via the calibration load board. ### Claim 6 (depends on 5) The system of claim 5, wherein a loopback function is provided by outputting the received data pattern through signal ports of the device under test and transmitting the outputted signals back to the BERT through the buses of the electrical validation board, the compliance load board and the inter-symbol interference board. ### Claim 7 (depends on 1) The system of claim 1, wherein the data pattern provided to the electronic device under test causes the generation of stressed eye signals at the electronic device under test. ### Claim 8 A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT), comprising: configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate. ### Claim 9 (depends on 8) The method of claim 8, wherein configuring the BERT comprises configuring the BERT to run an equalization protocol to train the electronic device under test to obtain one or more of an optimal decision feedback equalization tap setting and an optimal continuous time linear equalization tap setting for the inter-symbol interference channel. ### Claim 10 (depends on 8) The method of claim 8, further including selecting a data trace from a number of data traces of an electrical validation board into which the electronic device under test is connected for testing, the data traces having different lengths, the selected data trace forming part of the inter-symbol interference channel to introduce a desired delay for creation of the desired receiver stressed eye diagram at the electronic device under test. ### Claim 11 (depends on 10) The method of claim 10, wherein the loopback mode comprises transmitting the data pattern to the electronic device under test from the BERT via the selected data trace of the electrical validation board and the electronic device under test transmitting the received data pattern back to the BERT via the selected data trace of the electrical validation board. ### Claim 12 (depends on 8) The method of claim 8, further including selecting a data trace from a number of data traces of an inter-symbol interference board disposed between the BERT and the electronic device under test, the data traces having different lengths, the selected data trace forming part of the inter-symbol interference channel to introduce a desired delay for creation of the desired receiver stressed eye diagram at the electronic device under test. ### Claim 13 (depends on 12) The method of claim 12, wherein the loopback mode comprises transmitting the data pattern to the electronic device under test from the BERT via the selected data trace of the inter-symbol interference board and the electronic device under test transmitting the received data pattern back to the BERT via the selected data trace of the inter-symbol interference board. ### Claim 14 (depends on 8) The method of claim 8, wherein the data pattern provided to the electronic device under test by the BERT causes the generation of stressed eye signals at the electronic device under test. ### Claim 15 A system for calibrating a receiver stressed eye signal using a bit error rate tester (BERT), comprising: a calibration base board having data traces and data strobe traces; a calibration load board adapted to connect to the data traces and data strobe traces of the calibration base board to receive a data pattern with jitter and noise injected from the BERT; and an oscilloscope connected to the data traces and data strobe traces of the calibration base board to display the stressed eye signal received from the BERT, wherein the data pattern is provided to the oscilloscope over one or more of data traces and data strobe traces having varied lengths to provide different delay and inter-symbol interference effects for display by the oscilloscope. ### Claim 16 (depends on 15) The system of claim 15, wherein the data traces and the data strobe traces of the calibration base board have varied lengths. ### Claim 17 (depends on 15) The system of claim 15, wherein the data traces and data strobe traces of the calibration base board are of equal length, further comprising an inter-symbol interference board disposed between the BERT and the calibration load board which receives the data pattern from the BERT, the inter-symbol interference board having data traces of varied lengths to provide the different delay and inter-symbol interference effects to the oscilloscope via the calibration load board and calibration base board. ### Claim 18 (depends on 15) The system of claim 15, wherein the data pattern provided to the electronic device under test causes the generation of stressed eye signals for display on the oscilloscope. ### Claim 19 (depends on 15) The system of claim 15, wherein the oscilloscope steps through receiver continuous time linear equalization settings to obtain an optimal transmitter preset. ### Claim 20 (depends on 15) The system of claim 15, wherein an input of the oscilloscope is directly connected to a transmit channel of the BERT so as to receive random jitter and sinusoidal jitter levels of transmit signals from the BERT set to nominal values described in prescribed design specifications for the electronic device under test.