Direct Sensing BioFETs and Methods of Manufacture

A method of making a BioFET integrated circuit, comprising:

• forming a first FET and a second FET on a semiconductor substrate, the first and second FETs having respective gate structures;
• depositing a dielectric layer over the first and the second FET;
• patterning the dielectric layer to expose the gate structure of the first FET while leaving unexposed the gate structure of the second FET;
• forming a sacrificial plug contacting the gate structure of the first FET;
• forming a multi-layer interconnect (MLI) over the first and second FETs;
• patterning the MLI to expose at least a portion of the sacrificial plug and the gate structure of the first FET to form a first well portion;
• and
• removing the at least a portion of the sacrificial plug and the gate structure of the first FET to form a second well portion, while leaving the gate structure of the second FET intact.

A method of making a BioFET device, comprising:

• forming a FET on a semiconductor substrate, wherein the FET includes a gate dielectric, a gate electrode overlying the gate dielectric, and a spacer on a sidewall of the gate electrode;
• lining the gate electrode and the spacer with a protective layer;
• depositing a dielectric layer covering the gate electrode and the spacer;
• exposing a portion of the gate electrode by patterning the dielectric layer using a first etch process and patterning the protective layer using a second etch process;
• forming a sacrificial plug on and contacting the exposed portion of the gate electrode;
• depositing at least one second dielectric layer directly over the sacrificial plug;
• patterning the at least one second dielectric layer and the dielectric layer to form a first well portion having a first cross-section area, the first well portion exposing the sacrificial plug;
• removing at least a portion of the sacrificial plug, the gate electrode, and the gate dielectric to form a second well portion having a second cross-sectional area less than the first cross-sectional area;
• and
• depositing a replacement gate dielectric on a bottom of the second well portion.