Enclosure-to-board interface with tamper-detect circuit(s)

A tamper-respondent assembly comprising:

• a circuit board;
• at least one electronic component to be protected, the at least one electronic component being associated with the circuit board;
• an enclosure mounted to the circuit board along an enclosure-to-board interface, the enclosure facilitating enclosing the at least one electronic component within a secure volume;
• a tamper-respondent electronic circuit structure facilitating defining the secure volume, the tamper-respondent electronic circuit structure comprising one or more tamper-detect circuits comprising at least one conductive trace disposed, at least in part, within the enclosure-to-board interface, the at least one conductive trace comprising stress rise regions to facilitate detecting a tamper event at the enclosure-to-board interface;
• and
• an adhesive securing the enclosure to the circuit board, the adhesive contacting, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface, including at the stress rise regions of the at least one conductive trace.

A fabrication method comprising:

• fabricating a tamper-respondent assembly, the fabricating comprising:
• providing a circuit board;
• providing an enclosure mounted to the circuit board along an enclosure-to-board interface, the enclosure facilitating enclosing at least one electronic component coupled to the circuit board within a secure volume;
• providing a tamper-respondent electronic circuit structure facilitating defining the secure volume, the tamper-respondent electronic circuit structure comprising one or more tamper-detect circuits comprising at least one conductive trace disposed, at least in part, within the enclosure-to-board interface, the at least one conductive trace comprising stress rise regions to facilitate detecting a tamper event at the enclosure-to-board interface;
• and
• securing the enclosure to the circuit board using an adhesive, the adhesive contacting, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface, including at the stress rise regions of the at least one conductive trace.