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US 2020/0007350 A1Published application
Two bit/cell sram puf with enhanced reliability
AssigneeBirad—Research & Development Company Ltd.
InventorsYitzhak Shifman, Avi Miller, Joseph Shor
Life of this patent
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Abstract
A method for detecting unreliable bits in transistor circuitry includes adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit. The adjusting includes tilting the PUF cell to either a zero or one state: if the PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.
Claims14
A method for detecting unreliable bits in transistor circuitry comprising:
- adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit, wherein the adjusting comprises tilting the PUF cell to either a zero or one state, and if said PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.
A circuit comprising:
- a static random-access memory (SRAM) PUF cell having two or more bits per cell and which comprises two crisscrossed inverters, wherein a first inverter has its input coupled to a node H and its output coupled to a node H_b, and a second inverter has its input coupled to the node H_b and its output coupled to the node H, and the nodes H and H_b are initialized to either Vss or Vcc.
Dependencies are inferred from the claim text.