Use of Differently Delayed Feedback to Suppress Metastability in Noise Shaping Control Loops
AssigneeSiliconIntervention Inc.
InventorA. Martin Mallinson
Life of this patent
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Abstract
Described herein is a ΣΔ modulator with improved metastability in which the control loop remains stable. In one embodiment, the ΣΔ modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero.
Claims21
An apparatus, comprising:
- a first comparator configured to receive an input signal and a first feedback signal, and to generate a first error signal that is the difference between the input signal and the first feedback signal;
- a first integrator configured to receive and integrate the first error signal;
- a second comparator configured to receive the integrated error signal from the first integrator and a second feedback signal, and to generate a second error signal that is the difference between the integrated first error signal and the second feedback signal;
- a second integrator configured to receive and integrate the second error signal;
- a first quantizer configured to receive the integrated second error signal from the second integrator and to generate an output signal;
- a feedback loop for generating the first feedback signal and the second feedback signal, comprising:
- a digital to analog converter configured to receive the output signal and generate a modified output signal;
- a second quantizer configured to receive the modified output signal and generate a quantized modified output signal;
- a first weighting element configured to receive and weight the quantized modified output signal to generate the first feedback signal;
- a second weighting element configured to receive and weight the modified output signal to generate the second feedback signal.
An apparatus, comprising:
- a first comparator configured to receive an input signal and a first feedback signal, and to generate a first error signal that is the difference between the input signal and the first feedback signal;
- a first integrator configured to receive and integrate the first error signal;
- a second comparator configured to receive the integrated error signal from the first integrator and a second feedback signal, and to generate a second error signal that is the difference between the integrated first error signal and the second feedback signal;
- a second integrator configured to receive and integrate the second error signal;
- a third comparator configured to receive the integrated error signal from the second integrator and a third feedback signal, and to generate a third error signal that is the difference between the integrated second error signal and the third feedback signal;
- a third integrator configured to receive and integrate the third error signal;
- a first quantizer configured to receive the integrated third error signal from the third integrator and to generate an output signal;
- a feedback loop for generating the first feedback signal and the second feedback signal, comprising:
- a digital to analog converter configured to receive the output signal and generate a modified output signal;
- a second quantizer configured to receive the modified output signal and generate a quantized modified output signal;
- a first weighting element configured to receive and weight the quantized modified output signal to generate the first feedback signal;
- a second weighting element configured to receive and weight the quantized modified output signal to generate the second feedback signal;
- a third weighting element configured to receive and weight the modified output signal to generate the third feedback signal.
An apparatus, comprising:
- a first comparator configured to receive an input signal and a first feedback signal, and to generate a first error signal that is the difference between the input signal and the first feedback signal;
- a first integrator configured to receive and integrate the first error signal;
- a second comparator configured to receive the integrated error signal from the first integrator and a second feedback signal, and to generate a second error signal that is the difference between the integrated first error signal and the second feedback signal;
- a second integrator configured to receive and integrate the second error signal;
- a third comparator configured to receive the integrated error signal from the second integrator and a third feedback signal, and to generate a third error signal that is the difference between the integrated second error signal and the third feedback signal;
- a third integrator configured to receive and integrate the third error signal;
- a first quantizer configured to receive the integrated third error signal from the third integrator and to generate an output signal;
- a feedback loop for generating the first feedback signal and the second feedback signal, comprising:
- a digital to analog converter configured to receive the output signal and generate a modified output signal;
- a second quantizer configured to receive the modified output signal and generate a quantized modified output signal;
- a third quantizer configured to receive the quantized modified output signal and generate a further quantized modified output signal;
- a first weighting element configured to receive and weight the further quantized modified output signal to generate the first feedback signal;
- a second weighting element configured to receive and weight the quantized modified output signal to generate the second feedback signal;
- a third weighting element configured to receive and weight the modified output signal to generate the third feedback signal.
Dependencies are inferred from the claim text.