Soft error-resilient latch

A method, comprising:

• storing a plurality of data bits in a respective plurality of storage nodes of a latch, each data bit of the plurality of data bits being stored in a respective storage node of the plurality of storage nodes;
• determining, by a first multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs respectively coupled to two other storage nodes of the plurality of storage nodes, whether two respective states of two data bits stored in the two other storage nodes, respectively, changed;
• in response to determining that the two respective states changed, causing a state of a data bit stored in the storage node to change;
• and
• in response to determining that one of the two respective states or none of the two respective states changed, refraining from causing the state of the data bit stored in the storage node to change.

A latch, comprising:

• a supply voltage node;
• a reference voltage node;
• a plurality of storage nodes including a first, second and third storage nodes;
• and
• a plurality of supply voltage multi-dependency stages including a first supply voltage multi-dependency stage, the first supply voltage multi-dependency stage including a first supply transistor and a second supply transistor, the first supply transistor having a first conduction terminal coupled to the first storage node, a control terminal coupled to the second storage node and a second conduction terminal, the second supply transistor having a first conduction terminal coupled to the second conduction terminal of the first supply transistor, a control terminal coupled to the third storage node and a second conduction terminal coupled to the supply voltage node;
• and
• a plurality of reference voltage multi-dependency stages including a first reference voltage multi-dependency stage, the first reference voltage multi-dependency stage including a first reference transistor and a second reference transistor, the first reference transistor having a first conduction terminal coupled to the first storage node, a control terminal coupled to the second storage node and a second conduction terminal, the second reference transistor having a first conduction terminal coupled to the second conduction terminal of the first reference transistor, a control terminal coupled to the third storage node and a second conduction terminal coupled to the reference voltage node.