US 2020/0007113 A1 · SPECTRALLY EFFICIENT DIGITAL LOGIC

Abstract

Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for combinatorial or sequential logic elements and circuits. A SEDL circuit includes a multiplier circuit configured to receive a clock signal and provide a product of the input signal and a clock signal, an integrator circuit to integrate the product signal over a first portion of a clock period to determine the logic state of the input signal, a limit circuit configured to apply limits to a state result provided to the integrator circuit, and a pulse generator configured to receive the logic state from the limit circuit and provide and output signal having a Gaussian-shaped output pulse that represents that logic value corresponding to the logic value of the input signal.

Claims21

Dependent claims

In a circuit, a method to assess a state of an incoming bit, the method comprising:

receiving an input signal;
receiving a clock signal;
obtaining a product signal from the product of the input and clock signals;
integrating the product signal over a first portion of a clock period of the clock signal to determine a logic state of the input signal, the first portion of the clock period being less than the clock period of the clock signal;
providing the determined logic state to a pulse generator;
and
providing an output signal having a spectrally-efficient-shape at an output of the pulse generator, wherein the spectrally-efficient-shaped output signal represents a logic value corresponding to the logic value of the input signal.

4 more elements

Dependencies are inferred from the claim text.

Spectrally efficient digital logic

Life of this patent

Spectrally efficient digital logic

Life of this patent

Abstract

Claims21