Thermal dispersion layer in programmable metallization cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFa-Shen Jiang, Hsing-Lien Lin
Life of this patent
Estimating the term…
Abstract
Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer.
Claims20
A memory device, comprising:
- a bottom electrode;
- a dielectric layer disposed over the bottom electrode;
- a top electrode disposed over the dielectric layer, wherein a conductive bridge is selectively formable within the dielectric layer to couple the bottom electrode to the top electrode;
- and
- a heat dispersion layer disposed between the bottom electrode and the dielectric layer.
A memory device comprising:
- a programmable metallization cell disposed over an interconnect wire, wherein the programmable metallization cell comprises a metal ion reservoir disposed between a top electrode and a bottom electrode, wherein an electrolyte is disposed between the metal ion reservoir and the bottom electrode, wherein a heat dispersion layer is disposed between the bottom electrode and the electrolyte;
- and
- wherein the electrolyte comprises a conductive bridge region over the interconnect wire, wherein the conductive bridge region is defined between a top surface of the heat dispersion layer and a bottom surface of the metal ion reservoir, wherein a conductive bridge is formable and erasable within the conductive bridge region.
A method for manufacturing a memory device, comprising:
- forming a bottom electrode over an interconnect wire, wherein the interconnect wire is formed over a substrate;
- forming a heat dispersion layer over the bottom electrode;
- forming a dielectric layer over the heat dispersion layer;
- forming a metal layer over the dielectric layer;
- forming a top electrode over the metal layer;
- forming a masking layer over the top electrode, wherein the masking layer covers a center region of the top electrode, wherein the masking layer leaves a sacrificial portion of the top electrode exposed;
- performing a first etch process to remove a portion of the bottom electrode, heat dispersion layer, dielectric layer, metal layer, and top electrode below the sacrificial portion of the top electrode;
- and
- forming a sidewall spacer around the top electrode, metal layer, and a portion of the dielectric layer.
Dependencies are inferred from the claim text.