Vertical thin film transistors having self-aligned contacts

A method of fabricating an integrated circuit structure, the method comprising:

• forming a first source or drain contact above a substrate;
• forming a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;
• forming a channel material over and along sidewalls of the gate stack pedestal, the channel material further on the first source or drain contact;
• forming dielectric spacers adjacent portions of the channel material along the sidewalls of the gate stack pedestal and on a portion of the channel material on the first source or drain contact;
• patterning the channel material on the first source or drain contact to form a channel material layer using the dielectric spacers as a mask;
• and
• forming a second source or drain contact over a portion of the channel material layer over the gate stack pedestal by etching a conductive later, wherein the dielectric spacers are an etch stop during the etching.

An integrated circuit structure, comprising:

• a first source or drain contact above a substrate;
• a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;
• a channel material layer over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact;
• first dielectric spacers adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal, wherein the first dielectric spacers are passivating for the channel material layer;
• second dielectric spacers adjacent the first dielectric spacers, wherein the second dielectric spacers have a higher etch resistance than the first dielectric spacers;
• a second source or drain contact over a portion of the channel material layer over the gate stack pedestal.