Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor
AssigneeInternational Business Machines Corporation
InventorsAlexander Reznicek, Xin Miao, Jingyun Zhang, Choonghyun Lee
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Abstract
A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.
Claims18
A method of forming a semiconductor structure, the method comprising:
- forming a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on an isolation layer that is disposed on a substrate, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack, and wherein the substrate is composed of a first semiconductor material having a first bandgap, and the isolation layer is composed of a second semiconductor material having a second bandgap that is larger than the first bandgap, and further wherein the second semiconductor material is lattice matched to the first semiconductor material and is doped such that the second semiconductor material has semi-insulating properties;
- recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets;
- forming an inner spacer in each gap;
- forming a source/drain (S/D) region by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet;
- removing the sacrificial gate structure and each recessed sacrificial semiconductor material nanosheet;
- and
- forming a functional gate structure around exposed surfaces of each semiconductor channel material nanosheet.
Dependencies are inferred from the claim text.