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US 2020/0006565 A1Published application
FinFET Device and Method of Forming Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Hao Yeh, Fu-Ting Yen
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Abstract
A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
Claims20
A method comprising:
- forming a fin over a substrate;
- forming a dummy gate structure over the fin;
- removing a portion of the fin adjacent the dummy gate structure to form a first recess;
- depositing a stressor material in the first recess;
- removing at least a portion of the stressor material from the first recess;
- and
- after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
4 more elements
A method comprising:
- patterning a substrate to form a strip, the strip comprising a first semiconductor material;
- forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above a top surface of the isolation region;
- forming a dummy gate structure along sidewalls and along a first top surface of the upper portion of the strip;
- performing a first etching process on the strip to form a first recess in the strip adjacent to the dummy gate structure;
- forming a first dielectric material within the first recess;
- performing an anneal process on the first dielectric material, the first dielectric material providing a stress to the sidewalls of the first recess after the anneal process;
- removing the first dielectric material from the first recess;
- and
- epitaxially growing a source/drain region in the first recess.
6 more elements
A semiconductor device comprising:
- a first semiconductor fin over a substrate, the first semiconductor fin comprising a channel region and a recess adjacent the channel region;
- a gate stack overlying a channel region of the first semiconductor fin, wherein the channel region of the first semiconductor fin has a stress between about 2.5 GPa and about 4.0 GPa;
- and
- an epitaxial region disposed within the recess.
1 more element
Dependencies are inferred from the claim text.