Isolation schemes for gate-all-around transistor devices

An integrated circuit including at least one transistor, the integrated circuit comprising:

• a first body including semiconductor material;
• a gate structure wrapped around the first body, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the first body, the gate electrode including one or more metals;
• a source or drain region adjacent the body, the source or drain region including semiconductor material and a first dopant, the first dopant being one of n-type or p-type;
• a second body adjacent the source or drain region, such that the source or drain region is between the first and second bodies, the second body including semiconductor material and a second dopant, the second dopant being the other of n-type or p-type relative to the first dopant;
• and
• a structure wrapped around the second body.

A method of forming an integrated circuit including at least one transistor, the method comprising:

• forming a first body and a second body, the first and second bodies including semiconductor material;
• forming a gate structure around the first body, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the first body, the gate electrode including one or more metals;
• forming a source or drain region between the first and second bodies, the source or drain region including semiconductor material and a first dopant, the first dopant being one of n-type or p-type;
• adding, to the second body, one or more of oxygen, nitrogen, or a second dopant that is the other of n-type or p-type relative to the first dopant;
• and
• forming a structure around the second body.