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US 2020/0006554 A1Published application
Vfet cmos dual epitaxy integration
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
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Abstract
Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.
Claims15
A vertical field effect transistor complementary metal oxide (VFET CMOS) structure comprising:
- an n-type field effect transistor (NFET) region comprising:
- one or more vertically oriented fins extending from a substrate;
- a bottom source or drain (S/D) region comprising an epitaxially grown n-type doped semiconductor adjacent a lower portion of the one or more vertically oriented fins extending from the substrate;
- a p-type field effect transistor (PFET) region comprising:
- one or more vertically oriented fins extending from the substrate;
- a bottom S/D region comprising an epitaxially grown p-type doped semiconductor adjacent a lower portion of the one or more vertically oriented fins extending from the substrate, wherein a distance from the bottom S/D region comprising the epitaxially grown p-type doped semiconductor to an adjacent channel defined by the one or more vertically oriented fins in the PFET region is equal to a distance from the bottom S/D region comprising the epitaxially grown n-type doped semiconductor to an adjacent channel defined by the one or more vertically oriented fins in the NFET region;
- a shallow trench isolation region formed in the substrate separating the NFET region and the PFET region.
4 more elements
Dependencies are inferred from the claim text.