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US 2020/0006552 A1Published application
Vertical transistor contact for cross-coupling in a memory cell
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Terence B. Hook, Junli Wang
Life of this patent
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Abstract
According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A first fin is formed over the first doped region. A gate is formed alongside portions of the first fin. A void is created by removing the first fin to expose a portion of the first doped region. A metal is deposited in the void to create the contact.
Claims17
A method for forming a contact for a transistor, the method comprising:
- forming a first doped region over a semiconductor substrate;
- forming a first fin over the first doped region;
- forming a gate alongside portions of the first fin;
- creating a void by removing the first fin to expose a portion of the first doped region;
- and
- depositing a metal in the void to create the contact.
3 more elements
A method for forming a semiconductor device, the method comprising:
- forming a first doped layer region on a substrate;
- forming a source or a drain (S/D) in the first doped layer region;
- forming a plurality of vertical fins on the first doped layer region in which one of the plurality of vertical fins is a dummy fin;
- forming a gate around at least a portion of each of the plurality of vertical fins;
- growing an epitaxial layer on each of the plurality of vertical fins;
- selectively removing the dummy fin and the epitaxial layer grown on the dummy fin to form a void, wherein the void contacts the first doped layer region;
- and
- forming a bottom contact in the void, wherein the bottom contact operably couples the gate to the S/D.
5 more elements
17-20. (canceled)
Dependencies are inferred from the claim text.