Negative Capacitance Transistor with a Diffusion Blocking Layer

A semiconductor device, comprising:

• a channel region formed in a substrate;
• a gate dielectric layer located over the channel region, wherein the gate dielectric layer has a dielectric constant greater than a dielectric constant of silicon dioxide;
• an interfacial oxide layer disposed between the channel region and the gate dielectric layer;
• a diffusion blocking layer located over the gate dielectric layer, wherein the diffusion blocking layer and the gate dielectric layer contain different types of high-k dielectric materials;
• a ferroelectric layer located over the diffusion blocking layer, wherein the ferroelectric layer contains dopants, and wherein a material composition of the diffusion blocking layer is configured to be non-reactive with the dopants and to reduce dopant diffusion from the ferroelectric layer into the gate dielectric layer;
• and
• a metal gate electrode located over the ferroelectric layer;
• wherein the semiconductor device is a negative capacitance device.

A method of fabricating a semiconductor device, comprising:

• forming a dielectric layer over a channel region of a transistor;
• depositing a diffusion blocking layer over the dielectric layer;
• forming a ferroelectric layer over the diffusion blocking layer, wherein the ferroelectric layer contains dopants;
• and
• forming a gate electrode over the ferroelectric layer;
• wherein:
• one or more annealing processes occurs after the forming of the ferroelectric layer and before or during a formation of the gate electrode;
• and
• the diffusion blocking layer reduces dopant diffusion from the ferroelectric layer into the dielectric layer during the one or more annealing processes.