Transistor contact area enhancement

A semiconductor device, comprising:

• a semiconductor body that includes a surface;
• a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region includes a sub-region that includes a blanket dopant;
• a first conductive contact on the surface of the semiconductor body above the first region;
• a leakage barrier;
• and
• a second conductive contact on a bottom portion of the sub-region, wherein at least a portion of the second conductive contact is adjacent to at least a portion of the leakage barrier.

A system, comprising:

• a memory;
• and
• a processor coupled with the memory, wherein the processor includes a semiconductor device comprising:
• a semiconductor body that includes a surface;
• a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region includes a sub-region that includes a blanket dopant;
• a first conductive contact on the surface of the semiconductor body above the first region;
• a semiconductor-on-insulator (SOI) at a bottom of the first region;
• a pocket channel dopant (PCD) formed in the channel, wherein the PCD is adjacent to a first portion of the SOI;
• and
• a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

A method, comprising:

• forming a semiconductor body that includes a surface;
• forming a first region and a second region in the semiconductor body, wherein a channel region is defined in the semiconductor body between the first region and the second region;
• providing a blanket dopant in a sub-region of the second region;
• forming a first conductive contact on the surface of the semiconductor body above the first region;
• forming a semiconductor-on-insulator (SOI) at a bottom of the first region;
• providing a pocket channel dopant (PCD) in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI;
• and
• forming a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI and a second portion of the second conductive contact is adjacent to a second portion of the PCD.