Transistor with inner-gate spacer
AssigneeIntel Corporation
InventorsEN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
Life of this patent
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AssigneeIntel Corporation
InventorsEN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
Estimating the term…
Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.
An integrated circuit structure comprising:
An integrated circuit including at least one transistor, the integrated circuit comprising:
An integrated circuit structure comprising:
Dependencies are inferred from the claim text.