Transistors having gates with a lift-up region
AssigneeTexas Instruments Incorporated
InventorJun CAI
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.
Claims20
A transistor comprising:
- a semiconductor;
- a first drift layer formed in the semiconductor, the first drift layer having majority carriers of a first type;
- a drain region formed in the first drift layer, the drain region having majority carriers of the first type;
- a body region formed in the semiconductor, the body region having majority carriers of a second type;
- a source region formed in the body region, the source region having majority carriers of the first type;
- a shallow trench isolation region formed in the first drift layer and disposed between the drain region and the body region;
- a dielectric formed on the semiconductor;
- and
- a gate formed over the dielectric and having a lift-up region.
A transistor comprising:
- a semiconductor substrate;
- a first drift layer formed in the semiconductor substrate, the first drift layer having majority carriers of a first type;
- a drain region formed in the first drift layer, the drain region having majority carriers of the first type;
- a body region formed in the semiconductor, the body region having majority carriers of a second type;
- a source region formed in the body region, the source region having majority carriers of the first type;
- a shallow trench isolation region formed in the first drift layer and disposed between the drain region and the body region;
- and
- a doped region formed in the first drift layer, the doped region having majority carriers of the first type.
An integrated circuit, comprising:
- a semiconductor substrate;
- and
- a Laterally Diffused MOSFET (LD-MOSFET) located over the substrate, the LD-MOSFET transistor including:
- a dielectric-filled trench at a surface of the semiconductor substrate;
- a doped region of the semiconductor substrate adjacent the dielectric-filled trench, wherein the doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate;
- an oxide layer over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench, the oxide layer having a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.
Dependencies are inferred from the claim text.