Dielectric lining layers for semiconductor devices

A solid assembly, comprising:

• a carrier-doped semiconductor layer including mobile charges of a first polarity;
• a dielectric layer including localized charges of a second polarity opposite the first polarity;
• and
• an electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

A method of fabricating a solid-state device, comprising:

• providing a substrate including a carrier-doped semiconductor layer including mobile charges of a first polarity;
• providing a dielectric layer including localized charges of a second polarity opposite the first polarity;
• and
• providing an electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

A solid-state device, comprising:

• a substrate comprising a p-type metal-oxide-semiconductor (PMOS) layer and an n-type metal-oxide-semiconductor (NMOS) layer;
• a first dielectric layer adjacent to the PMOS layer and including first localized charges of negative polarity;
• a first gate electrode adjacent to the first dielectric layer and further adjacent to the substrate;
• a second dielectric layer adjacent to the NMOS layer and including second localized charges of positive polarity;
• and
• a second gate electrode adjacent to the second dielectric layer and further adjacent to the substrate.