Cavity spacer for nanowire transistors

An integrated circuit comprising:

• a base;
• a first transistor structure with a first source on the base, a first drain on the base, a first body of a first width extending over the base between the first source and the first drain, and a first gate structure wrapped around the first body between first and second end portions of the first body, wherein the first gate structure includes a first gate electrode and a first gate dielectric between the gate electrode and the first body;
• a second transistor structure with a second source on the base, a second drain on the base, a second body of a second width extending over the base between the second source and the second drain, and a second gate structure wrapped around the second body between first and second end portions of the second body, wherein the second gate structure includes a second gate electrode and a second gate dielectric between the gate electrode and the second body;
• a first spacer material in contact with the first gate structure above the first end portion of the first body, and in contact with the second gate structure above the first end portion of the second body;
• and
• a second spacer material below the first end portion of the first body and below the first end portion of the second body, the second spacer material adjacent the gate structure being colinear with the first spacer material adjacent the gate structure in the first transistor structure and in the second transistor structure.

A method of forming a nanowire transistor, the method comprising:

• providing a semiconductor structure with a fin on a base, the fin having a layer stack with alternating layers of a semiconductor material and a sacrificial material, the semiconductor structure also including a dummy gate electrode on the fin between a source region and a drain region of the fin;
• depositing a first layer of spacer material;
• removing the source region and drain region of the fin, leaving a portion of the layer stack under the dummy gate electrode;
• etching back the sacrificial material to define cavities below end portions of the semiconductor material in the portion of the layer stack under the dummy gate electrode;
• depositing a second spacer material in the cavities;
• etching the second spacer material to expose ends of the semiconductor material in the portion of the layer stack under the dummy gate electrode;
• and
• forming a replacement source and a replacement drain in contact with ends of the semiconductor material in the portion of the layer stack under the dummy gate electrode.