Nanosheet transistor gate structure having reduced parasitic capacitance
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
Life of this patent
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Abstract
Embodiments are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device on a substrate. The fabrication operations include, forming a channel stack over the substrate, wherein the channel stack include stacked and spaced apart channel nanosheets. A metal gate is formed adjacent to end regions of the channel stack and around and between the stacked and spaced apart channel nanosheets. A permanent dummy gate is formed above the channel stack.
Claims20
A method of fabricating a semiconductor device, the method comprising:
- performing fabrication operations to form a nanosheet field effect transistor device on a substrate, wherein the fabrication operations include:
- forming a channel stack over the substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;
- forming a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets;
- and
- forming a permanent dummy gate above the channel stack.
A nanosheet field effect transistor device comprising:
- a channel stack formed over a substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;
- a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets;
- and
- a permanent dummy gate formed above the channel stack.
Dependencies are inferred from the claim text.