Nanosheet transistor with robust source/drain isolation from substrate

An apparatus, comprising:

• a substrate structure having a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers, the substrate structure including at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;
• a u-shaped portion formed at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;
• a first liner disposed upon the u-shaped portion of the at least one trench;
• a second liner disposed on the first liner;
• a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity;
• a plurality of recesses disposed between the nanosheet layers, wherein the third liner is further disposed within the plurality of recesses to form a plurality of inner spacers between the nanosheet layers;
• a source/drain epitaxy disposed upon the bottom inner spacer;
• a gate material disposed between the nanosheet layers;
• an insulative cap disposed upon a top nanosheet of the plurality of nanosheets;
• an interlayer dielectric layer disposed upon the insulative cap;
• and
• at least one contact formed within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.