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US 2020/0006473 A1Published application
Tunnel field-effect transistor and method for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPeter RAMVALL, Gerben DOORNBOS, Matthias PASSLACK
Life of this patent
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Abstract
A device includes a first epitaxial layer, a second epitaxial layer, an interlayer, a gate dielectric layer, and a gate layer. The interlayer is between the first epitaxial layer and the second epitaxial layer. The gate dielectric layer is around the interlayer. The gate layer is around the gate dielectric layer and the interlayer. The interlayer is slanted with respect to a sidewall of the gate layer.
Claims21
A device, comprising:
- a first epitaxial layer;
- a second epitaxial layer;
- an interlayer between the first epitaxial layer and the second epitaxial layer;
- a gate dielectric layer around the interlayer;
- and
- a gate layer around the gate dielectric layer and the interlayer, wherein the interlayer is slanted with respect to a sidewall of the gate layer.
3 more elements
A device, comprising:
- a substrate;
- a fin over the substrate, the fin comprising a bottom portion comprising a first type semiconductor material, a top portion comprising a second type semiconductor material, and a middle portion comprising an interlayer between the first type semiconductor material and the second type semiconductor material, wherein the first type semiconductor material and the second type semiconductor material are of different conductivity types;
- a gate dielectric layer around sidewalls of the fin;
- and
- a gate layer around the gate dielectric layer, wherein a top surface of the fin is free from coverage of the gate layer.
2 more elements
17-20. (canceled)
A device, comprising:
- a substrate;
- a first epitaxial layer over the substrate, wherein the first epitaxial layer has a tapered top;
- an interlayer over the tapered top of the first epitaxial layer;
- a second epitaxial layer over the interlayer;
- a gate dielectric layer around the interlayer;
- and
- a gate conductor around the gate dielectric layer and the interlayer.
4 more elements
Dependencies are inferred from the claim text.